 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| SN74LS156 Dual 1-of-4 Decoder/ Demultiplexer The SN74LS156 is a high speed Dual 1-of-4 Decoder/ Demultiplexer. This device has two decoders with common 2-bit Address inputs and separate gated Enable inputs. Decoder "a" has an Enable gate with one active HIGH and one active LOW input. Decoder "b" has two active LOW Enable inputs. If the Enable functions are satisfied, one output of each decoder will be LOW as selected by the address inputs. The LS156 has open collector outputs for wired-OR (DOT-AND) decoding and function generator applications. The LS156 is fabricated with the Schottky barrier diode process for high speed and are completely compatible with all ON Semiconductor TTL families. http://onsemi.com LS156-OPEN-COLLECTOR LOW POWER SCHOTTKY * * * * * * Schottky Process for High Speed Multifunction Capability Common Address Inputs True or Complement Data Demultiplexing Input Clamp Diodes Limit High Speed Termination Effects ESD > 3500 Volts 16 1 PLASTIC N SUFFIX CASE 648 GUARANTEED OPERATING RANGES Symbol VCC TA VOH IOL Parameter Supply Voltage Operating Ambient Temperature Range Output Voltage - High Output Current - Low Min 4.75 0 Typ 5.0 25 Max 5.25 70 5.5 8.0 Unit V C V mA 16 1 SOIC D SUFFIX CASE 751B ORDERING INFORMATION Device SN74LS156N SN74LS156D Package 16 Pin DIP 16 Pin Shipping 2000 Units/Box 2500/Tape & Reel (c) Semiconductor Components Industries, LLC, 1999 110 December, 1999 - Rev. 0 Publication Order Number: SN74LS156/D SN74LS156 CONNECTION DIAGRAM DIP (TOP VIEW) VCC 16 Eb 15 Eb 14 A0 13 O3b 12 O2b 11 O1b 10 O0b 9 NOTE: The Flatpak version has the same pinouts (Connection Diagram) as the Dual In-Line Package. 1 Ea 2 Ea 3 A1 4 O3a 5 O2a 6 O1a 7 O0a 8 GND LOADING (Note a) PIN NAMES A0, A1 Ea, Eb Ea O0 - O3 Address Inputs Enable (Active LOW) Inputs Enable (Active HIGH) Input Active LOW Outputs HIGH 0.5 U.L. 0.5 U.L. 0.5 U.L. 10 U.L. LOW 0.25 U.L. 0.25 U.L. 0.25 U.L. 5 U.L. NOTES: a) 1 TTL Unit Load (U.L.) = 40 mA HIGH/1.6 mA LOW. LOGIC SYMBOL 12 13 3 14 15 E DECODER a 0 1 2 3 A0 A1 A0 A1 0 1 E DECODER b 2 3 7 6 5 4 9 10 11 12 VCC = PIN 16 GND = PIN 8 http://onsemi.com 111 SN74LS156 LOGIC DIAGRAM Ea Ea 1 2 13 A0 A1 3 14 Eb Eb 15 7 6 5 4 9 10 11 12 O0a O1a O2a O3a O0b O1b O2b O3b VCC = PIN 16 GND = PIN 8 = PIN NUMBERS FUNCTIONAL DESCRIPTION The LS156 is a Dual 1-of-4 Decoder/Demultiplexer with common Address inputs and separate gated Enable inputs. When enabled, each decoder section accepts the binary weighted Address inputs (A0, A1) and provides four mutually exclusive active LOW outputs (O0 - O3). If the Enable requirements of each decoder are not met, all outputs of that decoder are HIGH. Each decoder section has a 2-input enable gate. The enable gate for Decoder "a" requires one active HIGH input and one active LOW input (Ea*Ea). In demultiplexing applications, Decoder "a" can accept either true or complemented data by using the Ea or Ea inputs respectively. The enable gate for Decoder "b" requires two active LOW inputs (Eb*Eb). The LS155 or LS156 can be used as a 1-of-8 Decoder/Demultiplexer by tying Ea to Eb and relabeling the common connection as (A2). The other Eb and Ea are connected together to form the common enable. The LS156 can be used to generate all four minterms of two variables. These four minterms are useful in some applications replacing multiple gate functions as shown in Fig. a. The LS156 has the further advantage of being able to AND the minterm functions by tying outputs together. Any number of terms can be wired-AND as shown below. f = (E + A0 + A1) (E + A0 + A1) (E + A0 + A1) (E + A0 + A1) where E = Ea + Ea; E = Eb + Eb E A0 A1 E A0 A1 E A0 A1 E A0 A1 E O0 A0 A1 E O1 A0 A1 E O2 A0 A1 E O3 A0 A1 O0 O1 O2 O3 Figure a TRUTH TABLE ADDRESS A0 X X L H L H A1 X X L L H H ENABLE "a" Ea L X H H H H Ea X H L L L L O0 H H L H H H OUTPUT "a" O1 H H H L H H O2 H H H H L H O3 H H H H H L ENABLE "b" Eb H X L L L L Eb X H L L L L O0 H H L H H H OUTPUT "b" O1 H H H L H H O2 H H H H L H O3 H H H H H L H = HIGH Voltage Level L = LOW Voltage Level X = Don't Care http://onsemi.com 112 SN74LS156 DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol VIH VIL VIK IOH VO OL Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Current 0.25 Output LOW Voltage 0.35 IIH IIL ICC Input HIGH Current 0.1 Input LOW Current Power Supply Current - 0.4 10 0.5 20 V A mA mA mA IOL = 8.0 mA - 0.65 Min 2.0 0.8 - 1.5 100 0.4 Typ Max Unit V V V A V Test Conditions Guaranteed Input HIGH Voltage for All Inputs Guaranteed Input LOW Voltage for All Inputs VCC = MIN, IIN = - 18 mA VCC = MIN, VOH = MAX IOL = 4.0 mA VCC = VCC MIN, VIN = VIL or VIH per Truth Table VCC = MAX, VIN = 2.7 V VCC = MAX, VIN = 7.0 V VCC = MAX, VIN = 0.4 V VCC = MAX AC CHARACTERISTICS (TA = 25C) Limits Symbol tPLH tPHL tPLH tPHL tPLH tPHL Parameter Propagation Delay Address, Ea or Eb to Output Propagation Delay Address to Output Propagation Delay Ea to Output Min Typ 25 34 31 34 32 32 Max 40 51 46 51 48 48 Unit ns ns ns Figure 1 Figure 2 Figure 1 VCC = 5.0 V CL = 15 pF RL = 2.0 k Test Conditions AC WAVEFORMS VIN 1.3 V tPHL 1.3 V tPLH 1.3 V VIN 1.3 V tPHL 1.3 V tPLH 1.3 V VOUT 1.3 V VOUT 1.3 V Figure 1. Figure 2. http://onsemi.com 113 |
Price & Availability of SN74LS156D
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |